1. Field of the Invention
The present invention relates to sample and hold (S/H) circuits and their corresponding techniques for sampling analog signals and holding the sampled values, and in particular, to such circuits and techniques for sampling single-ended signals and holding such sampled signals as differential signals.
2. Description of the Related Art
Fully differential circuit architectures are widely used for many applications such as switched capacitor filters and analog-to-digital (A/D) converters. Important benefits of such architectures include increased noise immunity and power supply rejection, as well as automatic compensation for second order non-linearities such as capacitor voltage coefficients. However, "real world" applications involve signals which are more often single-ended. Hence, a single-ended-to-differential signal converter is usually used as an input stage.
Referring to FIG. 1, a typical conventional single-ended-to-differential signal converter used as the input stage for a S/H circuit in an A/D converter using complementary metal oxide semiconductor (CMOS) technology uses switched capacitor input and output circuits controlled by non-overlapping clock signals .phi.1 and .phi.2 to control MOS switches S1-S7 and S8-S10, respectively. During the sample phase of operation, i.e., during assertion of clock signal .phi.1, switches S1-S7 are closed and the input signal VINp-VINn is sampled on input capacitors C1 and C2. The input terminal corresponding to the "negative" input signal phase VINn is connected to the reference potential of the actual single-ended input signal VINp, which is usually circuit ground potential. This sample clock phase .phi.1 is also used to bias the inputs INp, INn of the operational amplifier (op-amp) A1 to a common mode input voltage VCOMin through switches S3, S4 and S5, as well as to set the common mode output voltage (additional circuitry not shown). Switches S6 and S7 are used during the sample phase to pre-charge output feedback capacitors C3 and C4 to a known voltage. If the input voltage is unipolar, the pre-charged values are set by two different reference voltages, VREFp, VREFn which introduce offset voltages and the inputs INp, INn of the op-amp A1 which are equal to half of the full input voltage scale.
During the hold phase of operation, i.e., during assertion of clock signal phase .phi.2, switches S8-S10 are closed. This causes the electrical charges accumulated by the input capacitors C1, C2 to be redistributed between them and the output feedback capacitors C3, C4, thereby maintaining a quasi-null differential voltage at the inputs INp, INn of the op-amp A1.
Referring to FIG. 1A, the phase relationships among the clock signals .phi.1, .phi.1', .phi.1", .phi.2 are shown. Clock phases .phi.1' and .phi.1" are successively delayed, overlapping versions of clock signal phase .phi.1, and are all non-overlapping with respect to clock signal phase .phi.2.
Referring to FIG. 2, a typical conventional design for the op-amp A1 has a cascode architecture, as shown. For a given level of power dissipation, this architecture has a large transconductance which is necessary for fast settling in high speed circuits. Also, because of non-dominant poles at very high frequencies, the op-amp A1 does not require separate compensation capacitors which consume circuit (i.e., silicon) area and increase power dissipation. However, such a telescopic circuit configuration has disadvantages in that the output voltage range is reduced and the input common mode voltage has a small range. If this results in an input common mode voltage which is too small, the biasing transistor M7 is pushed into its linear operating region and the bias current is thereby reduced. If the input common mode voltage is too large, the input gain transistors enter their linear operating regions which results in a reduced transconductance and output impedance, thereby degrading the open loop circuit gain. Further, optimization of the output linear operating range, as established by the bias voltages for the cascode devices M3-M6, reduces the acceptable input common mode voltage range.
Another problem with the circuit of FIG. 1 is the variation of the input common mode voltage during the hold phase of operation. Ideally, redistribution of the charges accumulated by sampling capacitors C1 and C2 when switch S8 is closed and nodes INp and INn have virtually the same potential (i.e., the input common mode) would mean that the common node AB settles to a voltage potential which is equal to the arithmetic average of the input sample voltages VINp, VINn, thereby leaving the input common mode voltage of the op-amp A1 unchanged.
Referring to FIGS. 3A and 3B, the equations which describe this charge balancing can be written using the equivalent circuits for the sample phase of operation (FIG. 3A) and the hold phase of operation (FIG. 3B) as follows: EQU Q.sub.AB =V.sub.in .multidot.Cd.sub.1 '+(V.sub.in -Vcom.sub.in).multidot.C.sub.1 -Vcom.sub.in .multidot.C.sub.2( 1) EQU Qin.sub.p =(Vcom.sub.in -V.sub.in).multidot.C.sub.1 +(Vcom.sub.in -Vref.sub.n).multidot.C.sub.3 ( 2) EQU Qin.sub.n =Vcom.sub.in .multidot.C.sub.2 +(Vcom.sub.in -Vref.sub.p).multidot.C.sub.4 ( 3) EQU Q.sub.AB +Q.sub.1 +Q.sub.2 -Q.sub.8 =V.sub.AB .multidot.(Cd.sub.1 "+Cd.sub.2 ")+(V.sub.AB -Vcom.sub.in ').multidot.(C.sub.1 +C.sub.2)(4) EQU Qin.sub.p +Q.sub.3 '+Q.sub.4 =(Vcom.sub.in '-V.sub.AB).multidot.C.sub.1 +(Vcom.sub.in '-Vout.sub.p).multidot.C.sub.3 ( 5) EQU Qin.sub.n +Q.sub.3 "+Q.sub.5 =(Vcom.sub.in '-V.sub.AB).multidot.C.sub.2 +(Vcom.sub.in '-Vout.sub.n).multidot.C.sub.4 ( 6)
where:
Q.sub.AB =total charge stored in nodes A and B during sample PA1 Qin.sub.p & Qin.sub.n =charges stored in nodes In.sub.p and In.sub.n, respectively, during sample PA1 Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 & Q.sub.5 =charge injection from MOS switches S1, S2, S3, S4 and S5, respectively, at turn-off (end of the sample phase) PA1 Q.sub.8 =charge absorbed from node AB by switch S.sub.8 at turn-on (beginning of the hold phase) PA1 Vcom.sub.in =common mode input voltage during sample phase PA1 Vcom.sub.in '=common mode input voltage during hold phase PA1 V.sub.AB =node AB voltage during hold phase PA1 Vref.sub.p & Vref.sub.n ="positive" and "negative" reference voltages, respectively, centered on the output common mode PA1 Cd.sub.1 '& Cd.sub.2 '=voltage dependent junction capacitances associated with switches S1 and S2, respectively, during the sample phase PA1 Cd.sub.1 "& Cd.sub.2 "=voltage dependent junction capacitances associated with switches S1 and S2, respectively, during the hold phase PA1 .DELTA.V.sub.com =signal dependent variation of input common mode voltage V.sub.com PA1 .epsilon..sub.2 =relative mismatch between capacitors C.sub.1 and C.sub.2 PA1 .epsilon..sub.4 =relative mismatch between capacitors C.sub.3 and C.sub.4
Solving Equations (1)-(6) with the additional condition of EQU Vout.sub.p +Vout.sub.n =Vref.sub.p +Vref.sub.n ( 7)
imposed by the output common mode feedback yields the input common mode voltage during the hold phase of operation as follows: ##EQU1##
High speed circuits require very large sampling switches (switches S1-S5 in the circuit of FIG. 1) in order to reduced the RC time constant of the sampling circuit and reduce the signal drop across the input dependent switch resistance. Such large switches when implemented in MOS technology have large associated capacitances Cd which are on the same order of magnitude as the sampling and hold capacitors C1-C4, and have large channel charges. Simulations have demonstrated an input common mode voltage variation of 300 millivolts or more for sampling capacitors C1, C2 of two picofarads and NMOS sampling switches S1, S2 with width and length dimensions of 400 microns and 0.8 microns, respectively. Such a voltage variation is unacceptable for most designs and will lead to a collapse of the op-amp input pair.
The circuit non-linearities are dominated by the second harmonic which is not cancelled as it would be in fully differential architectures. The signal-dependent charge injection Q1 into the common node AB by sampling switch S1 is attenuated by the symmetric arrangement of the capacitors C1-C4 only to the degree by which the input capacitors C1, C2 and the output capacitors C3, C4 are matched to one another. A first order error in the differential output voltage can be computed using equations (1)-(7) above, and has a signal-dependent term of the following form: ##EQU2## where: .DELTA.V.sub.out =first-order error in differential output voltage V.sub.out
Other error terms in the differential output signal can be compensated by various calibration and/or correction techniques, but the signal-dependent term, as set forth above in Equation (13), primarily determines the degree of non-linear distortion.
Accordingly, it would be desirable to have a sample and hold circuit architecture for converting single-ended signals to differential signals while avoiding the above-discussed problems.